DAS FEHLVERHALTEN VON FLIPFLOPS BEI ASYNCHRONEM BETRIEB. = LE COMPORTEMENT DEFECTUEUX DE BASCULES EN CAS DE FONCTIONNEMENT ASYNCHRONEWOLF G.1977; FREQUENZ; DTSCH.; DA. 1977; VOL. 31; NO 3; PP. 71-76; ABS. ANGL.; BIBL. 4 REF.Article

O MOZLIWOSCI OSLABIENIA WARUNKOW NA BRAK WYSCIGOW KRYTYCZNYCH W UKLADACH ASYNCHRONICZNYCH Z PRZERZUTNIKAMI = POSSIBILITE D'ABAISSER LES CONTRAINTES DUES AU MANQUE DE CHEMIN DANS LES CIRCUITS ASYNCHRONES AVEC FLIP-FLOPSSOSNOWSKI J.1979; ARCH. AUTOMAT. TELEMECH.; POL; DA. 1979; VOL. 24; NO 2; PP. 273-282; ABS. RUS/ENG; BIBL. 20 REF.Article

DIRECT IMPLEMENTATION OF ASYNCHRONOUS CONTROL UNITSHOLLAAR LA.1982; IEEE TRANSACTIONS ON COMPUTERS; ISSN 0018-9340; USA; DA. 1982; VOL. 31; NO 12; PP. 1133-1141; BIBL. 21 REF.Article

KRS- UND ESER-TECHNIK FUER DIE PRUEFUNG DIGITALER SCHALTUNGEN = KRS ET ESER TECHNIQUE POUR L'ESSAI DE CIRCUITS NUMERIQUESHERMANN L; WERRMANN G.1981; FEINGERAETETECHNIK; ISSN 0014-9683; DDR; DA. 1981; VOL. 30; NO 5; PP. 219-221; BIBL. 1 REF.Article

A MASKED-FAULT-FREE REALIZATION OF FAIL-SAFE ASYNCHRONOUS SEQUENTIAL CIRCUITS.MUKAI Y; TOHMA Y.1976; IN: F.T.C.S. 6. 1976 INT. SYMP. FAULT-TOLERANT COMPUT.; PITTSBURGH, PA.; 1976; LONG BEACH; INST. ELECTR. ELECTRON. ENG.; DA. 1976; PP. 69-74; BIBL. 16 REF.Conference Paper

USE OF MEMORIES AND PROGRAMMABLE LOGIC ARRAYS FOR ASYNCHRONOUS SEQUENTIAL CIRCUITSDITZINGER A; LIPP HM.1979; I.E.E.E. J. COMPUT. DIGIT. TECH.; GBR; DA. 1979; VOL. 2; NO 5; PP. 213-220; BIBL. 14 REF.Article

ON THE STABILITY-EQUATION FOR FLIPFLOPSBROWN FM.1978; COMPUTERS ELECTR. ENGNG; GBR; DA. 1978; VOL. 5; NO 2; PP. 167-169; BIBL. 3 REF.Article

REVOLUTIONARY DESIGNS FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS USING LSIMAKI GK; KEEL JL.sdANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING. 17/1979/MONTICELLO IL; USA; URBANA-CHAMPAIGN: UNIVERSITY OF ILLINOIS; DA. S.D.; PP. 996-1005; BIBL. 9 REF.Conference Paper

LES TRANSMISSIONS DE DONNEES. LE MODE ASYNCHRONE ET SES CIRCUITSROLLET JN.1981; MINIS ET MICROS; ISSN 0336-4585; FRA; DA. 1981; NO 137; PP. 73-78Article

DYNAMIC ANALYSIS OF INPUT SYNCHRONIZERS.MARINO LR.1977; IN: ANNU. ASILOMAR CONF. CIRCUITS, SYST., COMPUT. 10; PACIFIC GROVE, CALIF.; 1976; NORTH HOLLYWOOD, CALIF.; WESTERN PERIODICALS; DA. 1977; PP. 443-447; BIBL. 4 REF.Conference Paper

INPUT-OUTPUT RELATIONSHIP OF ASYNCHRONOUS CIRCUIT OPERATING IN SPIKE-FREE MODEFURUYA K; TOHMA Y.1977; SYST. COMPUTERS CONTROLS; USA; DA. 1977 PUBL. 1979; VOL. 8; NO 3; PP. 35-42; BIBL. 10 REF.Article

10th international symposium on asynchronous circuits and systems (ASYNC 2004)International symposium on asynchronous circuits and systems. 2004, isbn 0-7695-2133-9, 1Vol, XII-251 p, isbn 0-7695-2133-9Conference Proceedings

ON UNIVERSAL SINGLE TRANSITION TIME ASYNCHRONOUS STATE ASSIGNMENTSNANYA T; TOHMA Y.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 8; PP. 781-782; BIBL. 2 REF.Article

A NEW APPROACH TO THE DECOMPOSITION OF SEQUENTIAL SYSTEMS.CIOFFI G; COSTANTINI E; DE JULIO S et al.1977; DIGIT. PROCESS.; SWITZ.; DA. 1977; VOL. 3; NO 1; PP. 35-48; ABS. FR. ALLEM.; BIBL. 6 REF.Article

ANALYSE DES CIRCUITS LOGIQUES ASYNCHRONES. II. ACCESSIBILITE DES ETATS OPERATIONNELS ET INFLUENCE DES RETARDS DANS LES FILSVARSHAVSKIJ VI; KISHINEVSKIJ MA; TAUBIN AR et al.1982; IZVESTIJA AKEDEMII NAUK SSSR. TEHNICESKAJA KIBERNETIKA; ISSN 0002-3388; SUN; DA. 1982; NO 4; PP. 84-97; BIBL. 9 REF.Article

N-CHANNEL ASYNCHRONOUS ARBITER RESOLVES RESOURCE ALLOCATION CONFLICTSPETRIU E.1980; COMPUTER DESIGN; USA; DA. 1980; VOL. 19; NO 8; PP. 126-132; 4 P.; BIBL. 7 REF.Article

COMPTEUR A DECADE JUSQU'A 200 MHZBLATOV VV; SHERNYAEV NM.1978; PRIBORY TEKH. EKSPER.; SUN; DA. 1978; NO 5; PP. 103-106; BIBL. 2 REF.Article

ON THE REALIZATION OF HAZARDLESS ASYNCHRONOUS SEQUENTIAL CIRCUITSMASUYAMA H; AE T; YOSHIDA N et al.1977; SYST. COMPUTERS CONTROLS; USA; DA. 1977 PUBL. 1979; VOL. 8; NO 3; PP. 59-66; BIBL. 20 REF.Article

HAZARD ANALYSIS OF ASYNCHRONOUS CIRCUITS IN MULLER-BARTKY'S SENSE.NOZAKI A.1976; J. COMPUTER SYST.; U.S.A.; DA. 1976; VOL. 13; NO 2; PP. 161-171; BIBL. 4 REF.Article

ON THE THREE-VALUED SIMULATION OF DIGITAL SYSTEMS.MOR M.1976; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1976; VOL. 25; NO 11; PP. 1152-1156; BIBL. 5 REF.Article

ALEAS DANS LES RESEAUX LOGIQUES ASYNCHRONESCHEBOTAREV AN.1976; KIBERNETIKA, U.S.S.R.; S.S.S.R.; DA. 1976; NO 4; PP. 8-11; BIBL. 4 REF.Article

Experimental observation of simultaneous asynchronous oscillation in an oscillator containing an idler circuit and two resonatorsIIDA, Y; MORITA, M.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1984, Vol 67, Num 7, pp 371-372, issn 0387-236XArticle

Base minimale de réalisation des circuits séquentielsTSIRLIN, B. S.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1985, Num 2, pp 91-97, issn 0002-3388Article

ON A TERNARY MODEL OF GATE NETWORKS = UN MODELE TERNAIRE DE RESEAUX A PORTES LOGIQUESBRZOZOWSKI J; YOELI M.1979; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1979; VOL. 28; NO 3; PP. 178-184; BIBL. 10 REF.Article

METHODE DE SYNTHESE DES SEQUENCES CORRECTES POUR LES CIRCUITS LOGIQUESZVYAGIN VF; GOLYNICHEV VN; NEMOLOCHNOV OF et al.1979; AVTOMAT. VYCHISLIT. TEKH.; SUN; DA. 1979; NO 5; PP. 33-40; BIBL. 6 REF.Article